2027

Node Reduction via Targeted ODC-Based Wire Additions for AIG Optimization
Node Reduction via Targeted ODC-Based Wire Additions for AIG Optimization

Zhuofan Lin, Shiju Lin

Asia and South Pacific Design Automation Conference Conference

Tokyo, Japan

Node Reduction via Targeted ODC-Based Wire Additions for AIG Optimization

Zhuofan Lin, Shiju Lin

Asia and South Pacific Design Automation Conference Conference

Tokyo, Japan

2026

GPU-Accelearted Efficient Transduction for Logic Optimization
GPU-Accelearted Efficient Transduction for Logic Optimization

Zhuofan Lin, Shiju Lin

Design, Automation and Test in Europe Conference 2026 Conference

Verona, Italy

[paper] [code] [poster] [video]

2025

ReNoC-ML: Reliability-Aware Network-on-Chip Performance Modeling using Machine Learning
ReNoC-ML: Reliability-Aware Network-on-Chip Performance Modeling using Machine Learning

Zhuofan Lin, Yang Wei Lim, Yongfu Li, Fakhrul Zaman Rokhani

IEEE Asia Pacific Conference on Circuits and Systems 2025 Conference

Busan, Korea

[paper]

FCP-LLM: Functional Coverpoint Plan Generation Using LLM in Early Design Verification Stage
FCP-LLM: Functional Coverpoint Plan Generation Using LLM in Early Design Verification Stage

Zhuofan Lin, Zixian Guo, Chao Wang, Ruixin Zheng, Yuxin Ji, Yang Wei Lim, Yuhang Zhang, Fakhrul Zaman Rokhani, Yongfu Li

IEEE Asia Pacific Conference on Circuits and Systems 2025 Conference

Busan, Korea

[paper]

FCP-LLM: Functional Coverpoint Plan Generation Using LLM in Early Design Verification Stage

Zhuofan Lin, Zixian Guo, Chao Wang, Ruixin Zheng, Yuxin Ji, Yang Wei Lim, Yuhang Zhang, Fakhrul Zaman Rokhani, Yongfu Li

IEEE Asia Pacific Conference on Circuits and Systems 2025 Conference

Busan, Korea

[paper]

Descriptor: A Corpus of Synthesizable Verilog RTL Modules Dataset for EDA Research (CORE)
Descriptor: A Corpus of Synthesizable Verilog RTL Modules Dataset for EDA Research (CORE)

Kian Kit Cheah, Fu Qi Chua, Yunxiang Zhang, Zhuofan Lin, Yuxin Ji, Yuhang Zhang, Xinfei Guo, Harikrishnan Ramiah, Yongfu Li

IEEE Data Descriptions Journal

[paper] [code]

Descriptor: A Corpus of Synthesizable Verilog RTL Modules Dataset for EDA Research (CORE)

Kian Kit Cheah, Fu Qi Chua, Yunxiang Zhang, Zhuofan Lin, Yuxin Ji, Yuhang Zhang, Xinfei Guo, Harikrishnan Ramiah, Yongfu Li

IEEE Data Descriptions Journal

[paper] [code]